A 60GHz transformer coupled amplifier in 65nm digital CMOS

Author:

1 January 2010

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 15292517,p. 343-346
DOI:10.1109/rfic.2010.5477356

Abstract

A three stage transformer coupled amplifier for operation in the 57-64 GHz band is presented. The amplifier uses differential capacitive neutralization and low loss transformers to achieve a gain of 30 dB at 61 GHz. The amplifier has an output compression point of 7.5 dBm and a power added efficiency at 1dB compression of 9% at 57 GHz. The amplifier has been fabricated in digital CMOS and occupies an area of 0.055 mm².

Keywords

This publication has 4 references indexed in Scilit:

A 60GHz-band 1V 11.5dBm power amplifier with 11% PAE in 65nm CMOS
2009
17-dB-gain CMOS power amplifier at 60GHz
2008
60-GHz PA and LNA in 90-nm RF-CMOS
2006
A simple subcircuit extension of the BSIM3v3 model for CMOS RF design
IEEE Journal of Solid-State Circuits, 2000