A low-voltage wide-input CMOS comparator for sensor application using back-gate technique

This publication has 16 references indexed in Scilit:

• 1-V CMOS comparator for programmable analog rank-order extractor
  IEEE Transactions on Circuits and Systems I: Regular Papers, 2003
• A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 μm CMOS technology
  2002
• Dynamic characterisation of high-speed latchingcomparators
  Electronics Letters, 2000
• A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
  IEEE Journal of Solid-State Circuits, 1999
• CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters
  IEEE Journal of Solid-State Circuits, 1998
• Analysis of the behavior of a dynamic latch comparator
  IEEE Transactions on Circuits and Systems I: Regular Papers, 1998
• Offset reduction technique for use with high speedCMOS comparators
  Electronics Letters, 1996
• Design techniques for high-speed, high-resolution comparators
  IEEE Journal of Solid-State Circuits, 1992
• An offset reduction technique for use with CMOS integrated comparators and amplifiers
  IEEE Journal of Solid-State Circuits, 1992
• A custom integrated circuit comparator for high-performance sampling applications
  IEEE Transactions on Instrumentation and Measurement, 1992