Global routing and track assignment for flip-chip designs

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Abstract
This paper describes a solution for global routing and track assignment of flip-chip I/O nets. Voronoi Diagram (VD) is used to partition the open routing space and the geometrical properties of VD graph are exploited to create global routing channels with capacity and congestion considerations. A network flow algorithm is used to achieve optimal global routing. The regularity of the flip-chip bump placement is observed and allows us to reduce the size of global routing channel graph by over 50% to speed up computation. A track assignment algorithm avoids crossing wires before completing the final route with a detailed router. Experiment results using actual silicon chip data demonstrate that our solution achieves good quality of results compared to an implementation used in a commercial tool. Categories and Subject Descriptors: B.7.2 [Integrated Circuits]: Design Aids — Layout, Placement and Routing General Terms: Algorithms, Design
Funding Information
  • Ministry of Science and Technology of the People's Republic of China (2005CB321701, 8510700100)
  • Ministry of Education of the People's Republic of China (2.01E+11)
  • National Natural Science Foundation of China (60976034)

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