Abstract
In this work, a novel vertical gate-all-around field-effect transistor (VGAAFET) structure is proposed for scaling CMOS technology. Compared to the traditional VGAAFET, the lengths of gate ( ${L} _{g}$ ), spacer ( ${L} _{\text {sp}}$ ), and source/drain ( ${L} _{{\text S}/{\text D}}$ ) are predefined by the Si/SiGe/Si/SiGe/Si epitaxial stacks. Benefiting from the decoupling of the ${L} _{g}$ , ${L} _{\text {sp}}$ , and ${L} _{{\text S}/{\text D}}$ from the contact gate pitch (CGP) in the VGAAFET, the ${L} _{g}$ and ${L} _{\text {sp}}$ have been optimized to enhance the device performance without extending the footprint. To address the structural asymmetry and reduce the parasitic resistance ( ${R} _{\text {para}}$ ) of the VGAAFET, the backside contacts (BSCs) technology is integrated. Compared to the frontside contacts (FSCs) VGAAFET, the bottom source/drain resistance ( ${R} _{\text {BotS}/\text {D}}$ ) is reduced by 46.5%, and the on-state normalized current ( ${I} _{\text {on},\text {norm}}$ ) is increased by 21.8% for BSC-VGAAFET. Additionally, by employing the extension region doping (ERD) technology to improve the electrical characteristics symmetry between n/p VGAAFETs, an enhanced n/p current ratio from 1.31 to 1.16 has been achieved. Furthermore, to benchmark the power, performance, and area (PPA) characteristics between the VGAAFET and lateral GAAFET (LGAAFET) at the circuit-level, the nand2 standard cells are designed at the same footprint, and evaluated in our design technology co-optimization (DTCO) platform. The results of the 15-stage ring oscillator (RO) demonstrate that at the same supply voltage ( ${V} _{\text {dd}}$ ) and footprint, the BSC-VGAAFET achieves 52.2% frequency improvement and 21.6% energy-delay product (EDP) reduction compared to the LGAAFET. Therefore, the BSC-VGAAFET is a promising transistor architecture for next-generation integrated circuits (ICs).
Funding Information
  • National Key Research and Development Program of China (2023YFB4402203)

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