Vertical wrap-gated nanowire transistors
Authors:
- Tomas BryllertTBTomas Bryllert
- Lars-Erik WernerssonLWLars-Erik Wernersson
- Truls LöwgrenTLTruls Löwgren
- Lars SamuelsonLSLars Samuelson
- 19 May 2006
- journal article
- Published by IOP Publishing in Nanotechnology
- Vol. 17 (11) , S227-S230
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor ApplicationsIEEE Transactions on Nanotechnology, 2005
- Role of Surface Diffusion in Chemical Beam Epitaxy of InAs NanowiresNano Letters, 2004
- Nanowire Arrays Defined by Nanoimprint LithographyNano Letters, 2004
- Size-, shape-, and position-controlled GaAs nano-whiskersApplied Physics Letters, 2001
- Control of Thickness and Orientation of Solution-Grown Silicon NanowiresScience, 2000
- A Laser Ablation Method for the Synthesis of Crystalline Semiconductor NanowiresScience, 1998