Strategies for lot acceptance testing using CMOS transistors and ICs
Authors:
- J.R. SchwankJSJ.R. Schwank
- F.W. SextonFSF.W. Sexton
- D.M. FleetwoodDFD.M. Fleetwood
- M.R. ShaneyfeltMSM.R. Shaneyfelt
- K.L. HughesKHK.L. Hughes
- M.S. RodgersMRM.S. Rodgers
- 1 December 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 36 (6) , 1971-1980
Abstract
No abstract availableKeywords
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