Monitoring the Electrical Properties of the Back Silicon Interface of Silicon-on-Sapphire Wafers
Authors:
- Karl BertlingKBKarl Bertling
- Neal KistlerNKNeal Kistler
- George ImthurnGIGeorge Imthurn
- Michael StuberMSMichael Stuber
- Aleksandar D. RakicARAleksandar D. Rakic
- Yew-Tong YeowYYYew-Tong Yeow
- 21 March 2008
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 29 (4) , 325-327
Abstract
The density and the electrical nature of the interface traps at the silicon-sapphire interface of silicon-on-sapphire (SOS) MOSFETs have a significant influence on the electrical characteristics of these transistors. This letter describes a simple MOS test structure for evaluating the electrical properties of this interface of SOS wafers. Measurement and modeling of the C-V characteristics of the test structure fabricated on production SOS wafers are presented. We have demonstrated that the C-V characteristics are an efficient tool for studying the depletion of the silicon-sapphire interface by the interface trapped charge.Keywords
This publication has 6 references indexed in Scilit:
- UTSi CMOS: A Complete RF SOI SolutionAnalog Integrated Circuits and Signal Processing, 2000
- Adaptation of the pseudo-MOS transistor for the characterization of silicon-on-sapphire filmsSolid-State Electronics, 2000
- Characteristic electronic defects at the Si-SiO2 interfaceApplied Physics Letters, 1983
- Radiation-induced leakage currents in n-channel Silicon-on-sapphire MOST'sIEEE Transactions on Electron Devices, 1977
- On the origin of leakage currents in silicon-on-sapphire MOS transistorsIEEE Transactions on Electron Devices, 1977
- An investigation of the silicon—Sapphire interface using the MIS capacitance methodIEEE Transactions on Electron Devices, 1975