OpenTimer v2: A New Parallel Incremental Timing Analysis Engine
Authors:
- 7 July 2020
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 40 (4) , 776-789
Abstract
Since the first release in 2015, OpenTimer v1 has been used in many industrial and academic projects for analyzing the timing of custom designs. After four-year research and developments, we have announced OpenTimer v2—a major release that efficiently supports: 1) a new task-based parallel incremental timing analysis engine to break through the performance bottleneck of existing loop-based methods; 2) a new application programming interface (API) concept to exploit high degrees of parallelisms; and 3) an enhanced support for industry-standard design formats to improve user experience. Compared with OpenTimer v1, we rearchitect v2 with a modern C++ programming language and advanced parallel computing techniques to largely improve the tool performance and usability. For a particular example, OpenTimer v2 achieved up to $5.33\times $ speedup over v1 in incremental timing, and scaled higher with increasing cores. Our contributions include both technical innovations and engineering knowledge that are open and accessible to promote timing research in the community.Keywords
Funding Information
- NSF (CCF-1718883)
- Defense Advanced Research Projects Agency (FA 8650-18-2-7843)
This publication has 13 references indexed in Scilit:
- FastPass: Fast timing path search for generalized timing exception handling2018
- How Game Engines Can Inspire EDA Tools Development2017
- OpenDesign flow database: the infrastructure for VLSI design and design automation research2016
- UI-Timer 1.0: An Ultrafast Path-Based Timing Analysis Algorithm for CPPRIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016
- OpenTimer: A high-performance timing analysis tool2015
- iitRACE: A memory efficient engine for fast incremental timing analysis and clock pessimism removal2015
- TAU 2015 contest on incremental timing analysis2015
- iTimerC 2.0: Fast incremental timing and CPPR analysis2015
- ICCAD-2015 CAD contest in incremental timing-driven placement and benchmark suite2015
- A rank-one update method for efficient processing of interconnect parasitics in timing analysis2000