32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels

A local oscillator (LO) for 5G new radio requires sub-100fs rms jitter to support 64-OAM and $2\times2$ MIMO under non-ideal channel conditions [1]. Although fractional-N phase-locked loops (PLLs) employing digital-to-time converters (DTCs) and sampling phase detectors (SPDs) have demonstrated integrated jitter below 100fs [1, 2], such a DTC remains the most challenging block in this PLL architecture. It needs to achieve a fine resolution (e.g., 0.3ps) for low quantization noise (ON) and a large delay range to cancel the quantization error (OE) due to the delta-sigma modulator (DSM) used for fractional-N synthesis (e.g., 400ps for a5GHz VCO and mash1-1 DSM). The DTC also contributes to the in-band phase noise (PN) and its nonlinearity increases the fractional spur and noise folding. Reducing the DTC range alleviates the stringent design tradeoffs among PN, linearity, and design complexity [3]. This work presents a 6GHz fractional-N sampling PLL with a DTC range-reduction technique. With the modified multi-modulus divider (MMD) and the DSM that controls it, the accumulated OE at the MMD output is halved for any given order of the DSM. The same technique can also be applied to a charge-pump PLL or a digital PLL to ease the design of the phase detector. This PLL achieves 80fs rms jitter and -72dBc fractional spur at l4.2mW power consumption. lt also supports a low-power mode with 91.5fs rms jitter and consumes 8.2mW, offering power and jitter tradeoff.