Cosmos+ OpenSSD
Authors:
Open Access
- 16 July 2020
- journal article
- research article
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Storage
- Vol. 16 (3) , 1-35
Abstract
As semiconductor technology has advanced, many storage systems have begun to use non-volatile memories as storage media. The organization and architecture of storage controllers have become more complex to meet various design requirements in terms of performance, response time, quality of service (QoS), and so on. In addition, due to the evolution of memory technology and the emergence of new applications, storage controllers employ new firmware algorithms and hardware modules. When designing storage controllers, engineers often evaluate the performance impact of using new software and hardware components using software simulators. However, this technique often yields limited evaluation accuracy because of the difficulty of modeling complex operations of components and the interactions among them. In this article, we present a reconfigurable flash storage controller design that serves as a rapid prototype. This design can be synthesized into a field-programmable gate array device and used in a realistic performance evaluation environment. We show the usefulness of our design by demonstrating the performance impact of design parameters.Keywords
Funding Information
- R8D program of MOTIE/KEIT (10077609)
This publication has 20 references indexed in Scilit:
- uFLIP-OC2017
- Biscuit: A Framework for Near-Data Processing of Big Data Workloads2016
- A inversion-less peterson algorithm based shared KES architecture for concatenated BCH decoder2015
- Exploiting request characteristics and internal parallelism to improve SSD performance2015
- VSSIM: Virtual machine based SSD simulator2013
- Data Randomization Scheme for Endurance Enhancement and Interference Mitigation of Multilevel Flash Memory DevicesETRI Journal, 2013
- Physically addressed queueing (PAQ)ACM SIGARCH Computer Architecture News, 2012
- The gem5 simulatorACM SIGARCH Computer Architecture News, 2011
- A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical CommunicationsJournal of Signal Processing Systems, 2010
- 10- and 40-Gb/s forward error correction devices for optical communicationsIEEE Journal of Solid-State Circuits, 2002