A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension
Authors:
- Karyofyllis PatsidisKPKaryofyllis Patsidis
- Dimitris KonstantinouDKDimitris Konstantinou
- Chrysostomos NicopoulosCNChrysostomos Nicopoulos
- Giorgos DimitrakopoulosGiorgos Dimitrakopoulos
- 1 September 2018
- journal article
- research article
- Published by Elsevier in Microprocessors and Microsystems
- Vol. 61, 1-10
Abstract
No abstract availableKeywords
This publication has 1 reference indexed in Scilit:
- Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint DevicesIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017