A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining
Authors:
- A. PaparelliAPA. Paparelli
- G. PomichterGPG. Pomichter
- D.E. PontiusDPD.E. Pontius
- S. SlivaSSS. Sliva
- 3 January 2005
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 40 (1) , 213-222
Abstract
This work describes a 500-MHz compiled eDRAM macro offered in a 90-nm logic-based process. The macro architecture is optimized for high bandwidth while enabling compilation in bank and data-word dimensions. A direct write scheme simultaneously improves random bank cycle time and row access time without signal loss. The benefits of ground sensing, reference cells, and bitline twisting was reviewed. A variable stage pipeline extends the macro bandwidth while offering flexibility in clock frequencies. The redundancy system is modified to support direct write and piping. Finally, BIST was enhanced to utilize electrically blown fuses, enabling one-touch test and repair. Hardware results was presented.Keywords
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