Threshold electromigration failure time and its statistics for Cu interconnects

Integrated circuit chip metallization reliability under use conditions is extrapolated from failure distributions of test structures tested under accelerated conditions. Lognormally plotted electromigration failure time distributions for via/line contact configurations with no redundant conductive path usually display two features that are different from failure time distributions for configurations that have well-defined redundant conductive paths. First, the failure times are more widely distributed (larger standard deviation or $\sigma$ ), and second, the left portion of the distribution (early failures) bends downward (if the sample size is large enough) as the failure times become shorter, in contrast to the straight line behavior that is usually observed for structures with good redundancy. The downward deviation from a straight line distribution erodes the goodness of fit relative to the commonly used two-parameter $(t_{50},\sigma )$ lognormal distribution model, and the large $\sigma$ produces a lifetime projection under use conditions that can be unacceptable for chip reliability. A three-parameter lognormal distribution model $(t_{50},\sigma ,X_0)$ greatly improves the goodness of fit, especially for the downward bending early failure region, and produces projected failure times that are acceptable for chip reliability. The third parameter, $X_0$ , is interpreted as the threshold failure time for the distribution, or the time needed to form the absolute minimum size void that will cause failure. All recorded failure times for a given distribution will be greater than $X_0$ . Failure distributions for a via/line configuration with no redundancy are compared to those for via/line configurations with varying degrees and types of redundancy to demonstrate the behavior.