A 1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing
Authors:
- V. PrabhuVPV. Prabhu
- V. GeorgeVGV. George
- M. WanMWM. Wan
- M. BenesMBM. Benes
- A. AbnousAAA. Abnous
- J.M. RabaeyJRJ.M. Rabaey
- 1 November 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 35 (11) , 1697-1704
Abstract
A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. A 5.2 mm/spl times/6.7 mm prototype processor, targeted for voice compression, is implemented in a 0.25-/spl mu/m 6-metal CMOS process, and consumes 1.8 mW at an average operation rate of 40 MHz. It combines an embedded microprocessor with an array of computational units of different granularities, connected by a hierarchical reconfigurable interconnect network.Keywords
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