Flash ADC architecture
Authors:
- 20 March 2003
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 39 (6) , 501-502
Abstract
A 4-bit, 2.5 V modified flash analogue-to-digital converter (ADC) has been designed. In this design, the new flash topology only requires 2/sup (N-2)/+2 comparators. For comparison reasons, this new ADC architecture is operated at 400 MHz, consumes a total power of 1.68 mW and generates a total noise power of 4.86/spl times/10/sup -15/. /spl Delta/f(V/sup 2/) at this frequencyKeywords
This publication has 1 reference indexed in Scilit:
- Speed-power-accuracy tradeoff in high-speed CMOS ADCsIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2002