Low power design of FSMs by state assignment and disabling self-loops

This publication has 9 references indexed in Scilit:

• Automatic synthesis of low-power gated-clock finite-state machines
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996
• Low Power Design Methodologies
  1996
• Power estimation methods for sequential logic circuits
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995
• Logic extraction and factorization for low power
  1995
• Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs
  1995
• Precomputation-based sequential logic optimization for low power
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994
• Saving power by synthesizing gated clocks for sequential circuits
  IEEE Design & Test of Computers, 1994
• Circuit activity based logic synthesis for low power reliable operations
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993
• HYPER-LP: a system for power minimization using architectural transformations
  1992