100-Gb/s three-parallel Reed-Solomon based foward error correction architecture for optical communications
Authors:
- 1 November 2008
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 01, I-265-I-268
Abstract
This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-mum CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300 MHz and has a throughput of 115-Gb/s for 0.13-mum CMOS technology.Keywords
This publication has 6 references indexed in Scilit:
- A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon DecodersIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2008
- Two-parallel Reed-Solomon based FEC architecture for optical communicationsIEICE Electronics Express, 2008
- High-speed VLSI architecture for parallel Reed-Solomon decoderIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2003
- 10- and 40-Gb/s forward error correction devices for optical communicationsIEEE Journal of Solid-State Circuits, 2002
- The effect of error control coding in multichannel FSK coherent lightwave communication systems influenced by laser phase noiseJournal of Lightwave Technology, 1996
- A VLSI Design of a Pipeline Reed-Solomon DecoderIEEE Transactions on Computers, 1985