Layout techniques supporting the use of dual supply voltages for cell-based designs

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Abstract
Gate - level voltage scaling is an approach that allows different sup - ply voltages for different gates in order to achieve power reduction Previous researches focused on determining the voltage level for each gate and ascertaining the power saving capability of the ap - proach via logic - level power estimation In this paper, we present the layout techniques that feasiblize the approach in cell - based de - sign environment A new block layout style is proposed to support the voltage scaling with conventional standard cell libraries The block layout can be automatically generated via a simulated an - nealing based placement algorithm In addition, we propose a new cell layout style with built - in multiple supply rails Using the cell layout, gate - level voltage scaling can be immediately embedded in a typical cell - based design flow Experimental results show that proposed techniques produce very promising results