Cache Simulation for Instruction Set Simulator QEMU
Authors:
- Tran Van DungTDTran Van Dung
- Ittetsu TaniguchiITIttetsu Taniguchi
- Hiroyuki TomiyamaHTHiroyuki Tomiyama
- 1 August 2014
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 441-446
Abstract
In embedded system design, there is an increasing demand for modeling techniques that can provide both accurate measurements of delay and fast simulation speed. Modeling latency effects of a cache can greatly increase accuracy of the simulation and assist developers to optimize their software. Current solutions have not succeeded in balancing three important factors: speed, accuracy and usability. In this research, we created a cache simulation module inside a well-known instruction set simulator QEMU. Our implementation can simulate various cases of cache configuration and obtain every memory access. In full system simulation, speed is kept at around 73 MIPS on a personal host computer which is close to native execution of ARM Cortex-M3(125 MIPS at 100 MHz). Compared to the widely used cache simulation tool, Valgrind, our simulator is three time faster.Keywords
This publication has 4 references indexed in Scilit:
- Fast and Accurate Cache Modeling in Source-Level Simulation of Embedded Software2013
- Fast cycle estimation methodology for instruction-level emulator2012
- Using binary translation in event driven simulation for fast and flexible MPSoC simulation2009
- Cache Performance Simulation and Analysis under SimpleScalar Platform2009