Sub-60-nm quasi-planar FinFETs fabricated using a simplified process
Authors:
- L. ChangLCL. Chang
- Yang-Kyu ChoiYCYang-Kyu Choi
- E.H. AndersonEAE.H. Anderson
- Wen-Chin LeeWLWen-Chin Lee
- Tsu-Jae KingTKTsu-Jae King
- J. BokorJBJ. Bokor
- Chenming HuCHChenming Hu
- 1 October 2001
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 22 (10) , 487-489
Abstract
N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 μA/μm (or 1 mA/μm, depending on the definition of the width of the double-gate device) for V/sub g/-V T =V/sub d/=1 V. The electrical gate oxide thickness in these devices is 21 /spl Aring/, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness.Keywords
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