Energy aware scheduling for DAG structured applications on heterogeneous and DVS enabled processors
- 1 August 2010
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 495-502
Abstract
The trend towards ever more powerful and faster processors has led to an enormous increase in power consumption. This paper focuses on scheduling tasks in a heterogeneous environment with DVS enabled processors to minimize both execution time and energy consumed. The proposed algorithm, called Energy-Dynamic Level Scheduling (EDLS), favors low-energy consuming processors by introducing a cost factor that affects scheduling decisions. Our scheme allows for trade offs between energy consumption and the desired performance. Our simulation results exhibit significant power savings at a reasonable increase in overall execution time. Moreover, our results demonstrates a high degree of correlation between the energy saving and the increase in the heterogeneity of processors.Keywords
This publication has 11 references indexed in Scilit:
- The Challenges of Petascale ArchitecturesComputing in Science & Engineering, 2009
- Bounding energy consumption in large-scale MPI programs2007
- Power Aware Scheduling of Bag-of-Tasks Applications with Deadline Constraints on DVS-enabled Clusters2007
- Adaptive, Transparent Frequency and Voltage Scaling of Communication Phases in MPI Programs2006
- Scheduling with dynamic voltage/speed adjustment using slack reclamation in multi-processor real-time systems2005
- Dynamic, competitive scheduling of multiple DAGs in a distributed heterogeneous environment2002
- Matching and scheduling algorithms for minimizing execution time and failure probability of applications in heterogeneous computingIEEE Transactions on Parallel and Distributed Systems, 2002
- Performance-effective and low-complexity task scheduling for heterogeneous computingIEEE Transactions on Parallel and Distributed Systems, 2002
- A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architecturesIEEE Transactions on Parallel and Distributed Systems, 1993
- Low-power CMOS digital designIEEE Journal of Solid-State Circuits, 1992