A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS

Authors:

1 November 2011

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 69-72
DOI:10.1109/asscc.2011.6123606

Abstract

This paper presents a new subrange analog-to-digital converter (ADC): a binary-search coarse ADC + a SAR fine ADC. The binary-search ADC improves conversion speed and gives coarse capacitors longer settling time. This ADC uses an RC hybrid DAC to reduce the unit capacitor count by 2. The rotation function of coarse capacitors enhances capacitor array linearity. The prototype in 90-nm CMOS only occupies an active area of 0.06 mm². From a 0.9-V supply, the power consumption is 0.32 and 0.58 mW at 10 and 25 MS/s, respectively. At 10 MS/s, the peak ENOB is 10.2 bit. At 25 MS/s, the peak ENOB is 9.9 bit and FOM is 29 fJ/conversion-step.

Keywords

This publication has 3 references indexed in Scilit:

A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS
2010
A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC
2008
A 10-b, 500-MSample/s CMOS DAC in 0.6 mm/sup 2/
IEEE Journal of Solid-State Circuits, 1998