IEEE Standard for Verilog Hardware Description Language
- 12 December 2008
- standard
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 0_1-560
Abstract
The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.Keywords
This publication has 2 references indexed in Scilit:
- Description of a new variable-length key, 64-bit block cipher (Blowfish)1994
- A public key cryptosystem and a signature scheme based on discrete logarithmsIEEE Transactions on Information Theory, 1985