Rankings
Publications
Search Publications
Cited-by Search
Sources
Publishers
Scholars
Scholars
Top Cited Scholars
Organizations
About
Scilit
About Us
Advisory Board
Data Sources
Career
Support / Contact
User Guide
Publisher User
Search Function
Rankings Function
API Resource
Scilit Knowledge
Metrics
Scilit Recognitions
Publications Classification
Media
News
Blog
Login
Register
Home
Publications
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
Home
Publications
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
Authors:
MH
Michael Huebner
Michael Huebner
TB
Tobias Becker
Tobias Becker
JB
Juergen Becker
Juergen Becker
Article Alert
Citation Alert
Add to Library
Cite
Download
Share
Download
Download PDF
Download
Open Access
Publisher website
Google Scholar
4 September 2004
conference paper
Published by
Association for Computing Machinery (ACM)
p.
28-32
DOI:
10.1145/1016568.1016583
Abstract
No abstract available
Keywords
DYNAMIC PARTIAL RECONFIGURATION
VIRTEX
Cited
Cited by 55 articles
Scroll to top