A 9.0-TOPS/W Hash-Based Deep Neural Network Accelerator Enabling 128× Model Compression in 10-nm FinFET CMOS
- 25 August 2020
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Solid-State Circuits Letters
- Vol. 3, 338-341
Abstract
A 10nm DNN inference accelerator compresses model size with tabulation hash-based fine-grained weight sharing and increases 8b-compute density by 3.4× to 1.6 TOPS/mm2. The compressed model DNN implements lightweight hashing circuits to compress fully connected and recurrent neural networks. Optimized shared weight address generation reduces MUX tree area overhead by 40%. Runtime hash table generation and weight mapping circuits enable a peak energy efficiency of 9.0TOPS/W at 450mV, 25 ∘C. A 128×-compressed 3-layer LSTM classifies TIMIT phonemes with 85.6% accuracy for a total energy of 14μJ/classification, with <0.5% degradation in accuracy over an uncompressed network.Keywords
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- ESE2017