Assessment of the Electrical Performance of Short Channel InAs and Strained Si Nanowire FETs

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Abstract
We present a numerical study aimed to benchmark short gate InAs nanowire-FETs (NW-FETs) against their strained Si (sSi) counterpart. Our full-quantum simulations focus on both gate-length scaling and device variability and include the impact of electron-phonon scattering and surface roughness (SR). Interestingly, we found that SR improves the subthreshold-voltage swing (SS) of short gate-length InAs devices by inducing a reduced source-to-drain tunneling. Hence, InAs NW-FETs exhibit a larger immunity to the roughness-induced degradation of the ON-current, whereas they suffer from a larger OFF-current and SS variability with respect to the sSi ones. According to our results, InAs NW-FETs could compete with sSi NW-FETs only for very short gate lengths, when the device performance is significantly degraded, while for longer devices sSi NW-FETs remain a more effective and reliable choice due to the higher gate overdrive charge.
Funding Information
  • French Agence Nationale de la Recherche via the LabEx Minos (ANR-10-LABX-55-01)
  • NOODLES Project (ANR-13-NANO-0009-01)
  • MOSINAS Project (ANR-13-NANO-0001-04)
  • European Commission through the Compose3 Project and WayToGo Fast Project

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