Design Trade-Offs in VAX-11 Translation Buffer Organization

Authors:

M. Satyanarayanan
M. Satyanarayanan
DBD. Bhandarkar
D. Bhandarkar

1 December 1981

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in Computer

Vol. 14 (12) , 103-111
DOI:10.1109/c-m.1981.220301

Abstract

A major feature of the VAX-11 is its large virtual address space. This trace-driven simulation scheme evaluates address translation hardware that supports this feature cost-effectively.

Keywords

REGISTERS
OPERATING SYSTEMS
SWITCHES
MEMORY MANAGEMENT
HARDWARE
VIRTUAL PRIVATE NETWORKS
MICROCOMPUTERS
MEMORY ARCHITECTURE
CONTROL SYSTEMS
DATA STRUCTURES

This publication has 1 reference indexed in Scilit:

Cache memories for PDP-11 family computers
1976