Enhanced Performance and SRAM Stability in FinFET with Reduced Process Steps for Source/Drain Doping

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conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE) in 2008 International Symposium on Vlsi Technology, Systems and Applications (VLSI-TSA)

No. 1524766X,p. 20-21
DOI:10.1109/vtsa.2008.4530779

Abstract

Improved static noise margin in SRAM of 18% and decreased intrinsic inverter delay of 6% is demonstrated for the first time in double-gate CMOS finFET with gate- source/drain underlap doping. The excellent results are achieved by optimization of the spacer while simplifying the processing of source/drain region by skipping costly implants. Improved circuit and device performance with reduced processing steps make finFETs a more attractive option for 32 nm technology node and beyond.

Keywords

This publication has 4 references indexed in Scilit:

Highly Manufacturable Double-Gate FinFET With Gate-Source/Drain Underlap
IEEE Transactions on Electron Devices, 2007
Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era
IEEE Transactions on Electron Devices, 2007
Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs
IEEE Transactions on Nanotechnology, 2003
Speed superiority of scaled double-gate CMOS
IEEE Transactions on Electron Devices, 2002