SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design

This publication has 20 references indexed in Scilit:

• A cross-layer methodology for design and optimization of networks in 2.5D systems
  2018
• Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration
  2016
• uDIREC
  2013
• The cost study of 300mm through silicon interposer (TSI) with BEOL interconnect
  2013
• On effective TSV repair for 3D-stacked ICs
  2012
• End-to-end error correction and online diagnosis for on-chip networks
  2011
• Fault tolerant communication in 3D integrated systems
  2010
• Polarization Effect in Laser Processing of Fine Pitch Link Structures for Advanced Memory Designs
  IEEE Transactions on Semiconductor Manufacturing, 2009
• A survey of research and practices of Network-on-chip
  ACM Computing Surveys, 2006
• Hierarchical analysis of power distribution networks
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002