Bounding loop iterations for timing analysis
Authors:
- C. HealyCHC. Healy
- M. SjodinMSM. Sjodin
- V. RustagiVRV. Rustagi
- D. WhalleyDWD. Whalley
- 27 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 12-21
Abstract
No abstract availableThis publication has 11 references indexed in Scilit:
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