Impact of CMOS process scaling and SOI on the soft error rates of logic processes
Authors:
- J. MaizJMJ. Maiz
- M. AlaviMAM. Alavi
- K. MistryKMK. Mistry
- S. WalstaSWS. Walsta
- Changhong DaiCDChanghong Dai
- 13 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 73-74
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
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- The Los Alamos National Laboratory Spallation Neutron SourcesNuclear Science and Engineering, 1990