Transforming Group Codes in Mealy Finite State Machines with Composite State Codes
Open Access
- 13 April 2025
- journal article
- research article
- Published by MDPI AG in Applied Sciences
- Vol. 15 (8) , 4289
Abstract
A new state assignment method focusing on Mealy finite state machines (FSMs) is proposed. The proposed codes are an alternative to composite state codes (CSCs). CSCs are represented as concatenations of group codes and partial state codes. Both group and partial state codes are maximum binary codes. We propose encoding groups using one-hot codes. The main goal of this method is improving the value of the FSM cycle time without a significant degradation of the spatial characteristics. The method can be applied if FSM circuits are implemented using the look-up table (LUT) elements of field-programmable gate arrays (FPGAs). The resulting FSM circuit includes three logic blocks. The first block generates partial input memory functions and FSM outputs depending on maximum binary state codes and one-hot group codes. The partial codes are assigned in a way minimizing the number of arguments in the partial functions. This allows for the generation of most partial functions by single-LUT circuits. The second block generates the final values of the input memory functions and FSM outputs. This block does not require group codes to generate functions, as in CSC-based FSMs. The third block transforms maximum binary group codes into their one-hot equivalents. The proposed approach allows for a reduction in the number of series-connected LUTs in comparison with CSC-based FSMs. Due to this reduction, the temporal characteristics of an FSM circuit are improved. This paper includes an example of FSM synthesis applying the proposed method. The experiments were conducted using standard benchmark FSMs. The results of the experiments show that the proposed method allowed for an improvement in the cycle time of an average of 8.81%. Moreover, in relation to CSC-based FSMs, the LUT counts decreased by an average of 4.00%.Keywords
This publication has 26 references indexed in Scilit:
- State Machines using VHDL2021
- Technology Mapping for LUT-Based FPGA2021
- Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve CryptographyIEEE Access, 2020
- A Technology Mapping of FSMs Based on a Graph of Excitations and OutputsIEEE Access, 2019
- FPGA Structure2018
- Improving FPGA Performance with a S44 LUT Structure2018
- High-Performance Architecture for Binary-Tree-Based Finite State MachinesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017
- Logic synthesis for FPGAs based on cutting of BDDMicroprocessors and Microsystems, 2017
- Improvements to Technology Mapping for LUT-Based FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007
- Synthesis and Implementation of RAM-Based Finite State Machines in FPGAsLecture Notes in Computer Science, 2000