Demonstration of >8-kV GaN HEMTs With CMOS-Compatible Manufacturing on 6-in Sapphire Substrates for Medium-Voltage Applications

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Abstract
Traditional GaN HEMTs on silicon suffer relatively low lateral and vertical blocking voltages and thick buffers, which impede their use in $\boldsymbol {\ge }1.2$ -kV applications. In this work, the prototypes of 8-kV GaN HEMTs on 6-in sapphire are successfully fabricated using CMOS-compatible processing. An etch-stop nitride layer AlN in the in situ SiN cap precisely defines the gate dielectric thickness. Au-free low-temperature ohmic contact and metal I are achieved by Ti/AlCu/Ti/TiN, and gate metal is achieved by TiN/Ti/AlCu/Ti/TiN, which significantly reduces the material cost. The high mechanical strength of sapphire results in low nonuniformity and well-controlled warpage, enabling the use of a 1.5- $\boldsymbol {\mu }$ m buffer. The fabricated HEMTs with an ${L}_{\text {GD}}$ of $100~\boldsymbol {\mu }$ m exhibit a low ${R}_{\text {ON}}$ of $52~\boldsymbol {\Omega } \cdot $ mm and a stable ${V}_{\text {TH}}$ of −20 V. Benefiting from high-quality in situ SiN passivation, the dynamic ${R}_{\text {ON}}$ and ${V}_{\text {TH}}$ shift are maintained within 2.5% and 10%, respectively. The OFF-state breakdown voltage (BV) is increased beyond 8 kV using a simple device structure with only two field plates. The proposed low-cost and CMOS-compatible 8-kV GaN HEMTs fabricated on 6-in sapphire highlight an extremely simple epitaxy process, lateral device structure, and processing flow. Therefore, they offer great potential for serving future medium-voltage applications.
Funding Information
  • National Key Research and Development Program of China (2021YFB3600900)

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