High-Performance Robust Latches
Authors:
- 22 January 2010
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 59 (11) , 1455-1465
Abstract
First, a new high-performance robust latch (referred to as HiPeR latch) is presented that is insensitive to transient faults affecting its internal and output nodes by design, independently of the size of its transistors. Then, a modified version of the HiPeR latch (referred as HiPeR-CG) is proposed that is suitable to be used together with clock gating. Both proposed latches are faster than the latches most recently presented in the literature, while providing better or comparable robustness to transient faults, at comparable or lower costs in terms of area and power, respectively. Therefore, thanks to the good trade-offs in terms of performance, robustness, and cost, our proposed latches are particularly suitable to be adopted on critical paths.Keywords
This publication has 27 references indexed in Scilit:
- On the Scalability of Redundancy based SER Mitigation Schemes2007
- Selective node engineering for chip-level soft error rate improvement [in CMOS]2003
- Novel transient fault hardened static latch2003
- A logic-level model for α-particle hits in CMOS circuits2002
- A multigigahertz clocking scheme for the Pentium(R) 4 microprocessorIEEE Journal of Solid-State Circuits, 2001
- Soft errors in advanced semiconductor devices-part I: the three radiation sourcesIEEE Transactions on Device and Materials Reliability, 2001
- Impact of CMOS technology scaling on the atmospheric neutron soft error rateIEEE Transactions on Nuclear Science, 2000
- SEU testing of a novel hardened register implemented using standard CMOS technologyIEEE Transactions on Nuclear Science, 1999
- Upset hardened memory design for submicron CMOS technologyIEEE Transactions on Nuclear Science, 1996
- Soft errors induced by alpha particlesIEEE Transactions on Reliability, 1996