Skyrmion Logic-In-Memory Architecture for Maximum/Minimum Search
Open Access
- 12 January 2021
- journal article
- research article
- Published by MDPI AG in Electronics
- Vol. 10 (2) , 155
Abstract
In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with the performance gap between memory and logic, impacts heavily on algorithms performance, increasing the overall time and energy required for computation. A possible approach to overcome such limitations is Logic-In-Memory (LIM). In this paper, we propose a LIM architecture based on a non-volatile skyrmion-based recetrack memory. The architecture can be used as a memory or can perform advanced logic functions on the stored data, for example searching for the maximum/minimum number. The circuit has been designed and validated using physical simulations for the memory array together with digital design tools for the control logic. The results highlight the small area of the proposed architecture and its good energy efficiency compared with a reference CMOS implementation.Keywords
This publication has 28 references indexed in Scilit:
- Observation of room-temperature magnetic skyrmions and their current-driven dynamics in ultrathin metallic ferromagnetsNature Materials, 2016
- Gateable Skyrmion Transport via Field-induced Potential Barrier ModulationScientific Reports, 2016
- Mitigation of Magnus Force in Current-Induced Skyrmion DynamicsIEEE Transactions on Magnetics, 2015
- A strategy for the design of skyrmion racetrack memoriesScientific Reports, 2014
- The design and verification of MuMax3AIP Advances, 2014
- Nucleation, stability and current-induced motion of isolated magnetic skyrmions in nanostructuresNature Nanotechnology, 2013
- Skyrmions on the trackNature Nanotechnology, 2013
- Extended Skyrmion Phase in EpitaxialThin FilmsPhysical Review Letters, 2012
- Missing the memory wallACM SIGARCH Computer Architecture News, 1996
- Real-time maximum value determination on an easily testable VLSI architectureIEEE Transactions on Circuits and Systems I: Regular Papers, 1993