Power-Performance Advantages of InFO Technology for Advanced System Integration
Authors:
- 1 October 2019
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-4
Abstract
Novel InFO technologies have been developed to meet high bandwidth, low power consumption and small form factor requirements for system integration with key characteristics of thin dielectric layers, fine RDL lines, 3D vertical interconnects and multi-chip integration. The powerperformance advantages of the technology from the characteristics on power integrity (PI), signal integrity (SI) and RF are studied and compared to those of organic substrate technology. For PI, the InFO with IPD (Integrated Passive Device) has 56% lower of system power delivery networking (PDN) impedance and 25% lower of the 1st voltage droop. For SI, the effect of line width on data rate and line density is studied and a record high 10 Tbps/mm of bandwidth density is obtained by the submicron RDL on InFO. For RF system integration, a 3D solenoid inductor on InFO package is demonstrated. The 3D inductor with 3 turns achieves Q-factor (quality factor) of 59 at 3GHz and the simulation and measurement results are consistent. The power-performance study indicates the InFO is a wide-spectrum application technology.Keywords
This publication has 15 references indexed in Scilit:
- Signal and Power Integrity Analysis of InFO Interconnect for Networking Application2018
- A Novel Submicron Polymer Re-Distribution Layer Technology for Advanced InFO Packaging2018
- InFO (Wafer Level Integrated Fan-Out) Technology2016
- A Novel System in Package with Fan-Out WLP for High Speed SERDES Application2016
- High performance passive devices for millimeter wave system integration on integrated fan-out (InFO) wafer level packaging technology2015
- Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology2015
- A new integration technology platform: Integrated fan-out wafer-level-packaging for mobile applications2015
- 5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor2014
- Array antenna integrated fan-out wafer level packaging (InFO-WLP) for millimeter wave system applications2013
- A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging ApplicationsIEEE Journal of Solid-State Circuits, 2013