Subthreshold performance of gate engineered FinFET devices and circuit with high-k dielectrics
Authors:
- D. NirmalDND. Nirmal
- P. VijayakumarPVP. Vijayakumar
- Divya Mary ThomasDTDivya Mary Thomas
- Binola K. JebalinBJBinola K. Jebalin
- N. MohankumarNMN. Mohankumar
- 1 March 2013
- journal article
- research article
- Published by Elsevier in Microelectronics Reliability
- Vol. 53 (3) , 499-504
Abstract
No abstract availableKeywords
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