Unified Testing and Security Framework for Wireless Network-on-Chip Enabled Multi-Core Chips
Open Access
- 8 October 2019
- journal article
- research article
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Embedded Computing Systems
- Vol. 18 (5s) , 1-20
Abstract
On-chip wireless interconnects have been demonstrated to improve the performance and energy consumption of data communication in Network-on-Chips (NoCs). However, the wireless interfaces (WIs) can be defective, rendering these broken links severely affect the performance. This makes manufacturing test of the WIs critical. While analog testing of the transceivers is possible, such methodologies are impractical in a Wireless NoC (WiNoC) due to large overheads. In addition to testing, security is another prominent challenge in WiNoCs, as the security breach can happen due to embedded hardware Trojans or through external attacker exploiting the wireless medium. The typical security measures used in general wireless networks are not practical in a WiNoC due to unique network architectures and performance requirements of such a system. However, both testing and security defense can potentially leverage a basic monitoring framework which, can detect malfunctions or anomalies. Based on this idea, we propose a unified architecture for testing and attack detection and protection of on-chip wireless interconnects. We adopt a Built-In-Self Test (BIST) methodology to enable online monitoring of the wireless interconnects which can also be reused for monitoring the security threats. We focus on manufacturing defects of the WIs for testing and persistent jamming attack for the security measures, as this kind of attack is most likely on wireless communication systems. The BIST methodology is capable of detecting faults in the wireless links with a low aliasing probability of 2.32× 10 −10 . Additionally, the proposed unified architecture is able to detect the persistent jamming with an accuracy of 99.87% and suffer < 3% communication bandwidth degradation even in the presence of attacks from either internal or external sources.Keywords
Funding Information
- US National Science Foundation (NSF) CAREER (CNS-1553264)
This publication has 24 references indexed in Scilit:
- A Wireless Interconnection Framework for Seamless Inter and Intra-Chip Communication in Multichip SystemsIEEE Transactions on Computers, 2016
- IIPS: Infrastructure IP for Secure SoC DesignIEEE Transactions on Computers, 2014
- A 1.2-pJ/bit 16-Gb/s 60-GHz OOK Transmitter in 65-nm CMOS for Wireless Network-On-ChipIEEE Transactions on Microwave Theory and Techniques, 2014
- Performance evaluation and design trade-offs for wireless network-on-chip architecturesACM Journal on Emerging Technologies in Computing Systems, 2012
- A denial-of-service resilient wireless NoC architecture2012
- An Efficient Routing Protocol for Ad-Hoc Networks2011
- Using the Inter- and Intra-Switch Regularity in NoC Switch Testing2007
- Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect ArchitecturesIEEE Transactions on Computers, 2005
- Bringing communication networks on a chip: test and verification implicationsIEEE Communications Magazine, 2003
- Networks on chips: a new SoC paradigmComputer, 2002