Fabrication process development for superconducting VLSI circuits: minimizing plasma charging damage
Authors:
- S K TolpygoSTS K Tolpygo
- D AmparoDAD Amparo
- 1 February 2008
- conference paper
- Published by IOP Publishing in Journal of Physics: Conference Series
- Vol. 97
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- 20 ${\hbox{kA/cm}}^{2}$ Process Development for Superconducting Integrated Circuits With 80 GHz Clock FrequencyIEEE Transactions on Applied Superconductivity, 2007
- Parametric Testing of HYPRES Superconducting Integrated Circuit Fabrication ProcessesIEEE Transactions on Applied Superconductivity, 2007
- Temperature stability of thin anodic oxide films in metal/insulator/metal structures: A comparison between tantalum and aluminium oxideThin Solid Films, 2006
- Two breakdown mechanisms in ultrathin alumina barrier magnetic tunnel junctionsJournal of Applied Physics, 2004
- Tunneling properties of barriers in Nb/Al/AlO/sub x//Nb junctionsIEEE Transactions on Applied Superconductivity, 2003
- Plasma Charging Damage2001
- Modeling of oxide charging effects in plasma processingJournal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, 1996
- Plasma-charging damage: A physical modelJournal of Applied Physics, 1994
- Charging damage to gate oxides in an O2 magnetron plasmaJournal of Applied Physics, 1992
- RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systemsIEEE Transactions on Applied Superconductivity, 1991