Toward a systematic sensitivity analysis of on-chip power grids using factor analysis

Authors:

1 May 2007

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 155-158
DOI:10.1109/spi.2007.4512237

Abstract

We present a systematic way of performing sensitivity analysis on on-chip power distribution grids. By using factor analysis we are able to uncover correlations between power grid design variables and power supply noise. From our analysis of 300 different grids in a 65-nm process, we can identify which power grid design variables have both high correlation to and high impact on noise; the most important one being supply rail width.

Keywords

SENSITIVITY ANALYSIS
SYSTEM-ON-A-CHIP
POWER GRIDS
RAILS
POWER SUPPLIES
CIRCUIT NOISE
CAPACITANCE
LOGIC
PATTERN ANALYSIS
POWER DISTRIBUTION

This publication has 2 references indexed in Scilit:

Sensitivity analysis of generic on-chip ΔI-noise simulation methodology
2005
High-performance power grids for nanometer technologies
2004