A Reconfigurable Asynchronous SERDES for Heterogenous Chiplet Interconnects
Authors:
- 7 April 2021
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 542-546
Abstract
With advancing packaging technologies, multi-die integration is gaining prominence among players in the semiconductor industry for its ability to create a system with heterogenous functionalities (Digital Logic/High-speed I/O etc. at its most efficient process node) hence improving overall silicon yield. This work presents a source- synchronous die-to-die I/O using a self-timed loop (behaviorally analogous to a gated ring oscillator) that generates high-speed edges, eliminating any power-hungry PLL/DLLs found in traditional die-to-die I/O interfaces. In addition, the proposed asynchronous architecture enables easy reconfigurability of data rates under a small form factor and efficient design-reuse. The scheme achieves a maximum of 4.8Gbps/wire at 0.4pJ/b generating an effective shoreline bandwidth of 1.47Tbps/mm.Keywords
This publication has 9 references indexed in Scilit:
- Die to Wafer Stacking with Low Temperature Hybrid Bonding2020
- Multi-die Integration Using Advanced Packaging Technologies2020
- TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth In-Package Optical I/OIEEE Micro, 2020
- A Bunch of Wires (BoW) Interface for Inter-Chiplet Communication2019
- A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing2019
- Electrical Performance Limits of Fine Pitch Interconnects for Heterogeneous Integration2019
- Heterogeneous SoC Integration with EMIB2018
- Multi-chip technologies to unleash computing performance gains over the next decade2017
- A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects2017