Configuration compression for the Xilinx XC6200 FPGA
Authors:
- Zhiyuan LiZLZhiyuan Li
- E. SchwabeESE. Schwabe
- 1 August 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 18 (8) , 1107-1113
Abstract
One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting new paradigm. In this paper me explore one technique for reducing this overhead: the compression of configuration datastreams. We develop an algorithm, targeted to the decompression hardware imbedded in the Xilinx XC6200 series field-programmable gate array architecture, that can radically reduce the amount of data needed to transfer during reconfiguration. This results in an overall reduction of about a factor of four in total bandwidth required for reconfiguration.Keywords
This publication has 5 references indexed in Scilit:
- The roles of FPGAs in reprogrammable systemsProceedings of the IEEE, 1998
- Configuration prefetch for single context reconfigurable coprocessors1998
- Sequencing Run-Time Reconfigured Hardware with Software1996
- Configurable computing solutions for automatic target recognition1996
- Logic Minimization Algorithms for VLSI Synthesis1984