Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates

This publication has 28 references indexed in Scilit:

• Single Event Transient Suppressor for Flip-Flops
  IEEE Transactions on Nuclear Science, 2010
• Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm
  2009
• Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits
  IEEE Transactions on Dependable and Secure Computing, 2008
• Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies
  2007
• Soft error reduction in combinational logic using gate resizing and flipflop selection
  2006 IEEE/ACM International Conference on Computer Aided Design, 2006
• Design for soft error mitigation
  IEEE Transactions on Device and Materials Reliability, 2005
• Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor
  ACM SIGARCH Computer Architecture News, 2004
• IBM experiments in soft fails in computer electronics (1978–1994)
  IBM Journal of Research and Development, 1996
• A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results
  IEEE Transactions on Nuclear Science, 1995
• Polynomial Codes Over Certain Finite Fields
  Journal of the Society for Industrial and Applied Mathematics, 1960