A 0.5-3.5 Gb/s low-power low-jitter serial data CMOS transceiver
Authors:
- J.M. TranJTJ.M. Tran
- Heng-Chih LinHLHeng-Chih Lin
- Ah-Lyan YeeAYAh-Lyan Yee
- M. IzzardMIM. Izzard
- 20 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 352-353
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- A 1.0625 Gbps transceiver with 2x-oversampling and transmit signal pre-emphasis2002
- Low-jitter process-independent DLL and PLL based on self-biased techniquesIEEE Journal of Solid-State Circuits, 1996