Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices
- 1 December 2007
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1404-1407
Abstract
Leakage current is the main source of power dissipation in low-frequency digital circuits implemented in deep submicron processes. This contribution introduces a novel active-mode leakage reduction technique for ultra-low-power (ULP) low-frequency applications. It is based on the ULP CMOS logic style achieving negative-V GS self-biasing ULP logic gates have static current reduced by several orders of magnitude. For a commercial 0.13-μm technology, power consumption of ULP gates at low frequencies is lower than standard CMOS counterparts even considering high-V T devices, subthreshold operation and reverse body biasing. ULP gates are shown to be very stable against process, voltage and temperature variations.Keywords
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