Impact of the circuit layout on the charge collection in a monolithic pixel sensor
Open Access
- 1 June 2025
- journal article
- Published by IOP Publishing in Journal of Instrumentation
- Vol. 20 (06) , C06052
Abstract
CERN's strategic R&D programme on technologies for future experiments recently started investigating the TPSCo 65nm ISC CMOS imaging process for monolithic active pixels sensors for application in high energy physics. In collaboration with the ALICE experiment and other institutes, several prototypes demonstrated excellent performance, qualifying the technology. The Hybrid-to-Monolithic (H2M), a new test-chip produced in the same process but with a larger pixel pitch than previous prototypes, exhibits an unexpected asymmetric efficiency pattern. This contribution describes a simulation procedure combining TCAD, Monte Carlo and circuit simulations to model and understand this effect. It proved able to reproduce measurement results and attribute the asymmetric efficiency drop to a slow charge collection due to low amplitude potential wells created by the circuit layout and impacting efficiency via ballistic deficit.Keywords
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