A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme
Authors:
- S. TakaseSTS. Takase
- N. KushiyamaNKN. Kushiyama
- 1 January 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 34 (11) , 1600-1606
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode registerIEEE Journal of Solid-State Circuits, 1998
- Fault-tolerant designs for 256 Mb DRAMIEEE Journal of Solid-State Circuits, 1996
- A flexible redundancy technique for high-density DRAMsIEEE Journal of Solid-State Circuits, 1991