A study on a high blocking voltage UMOS-FET with a double gate structure
Authors:
- N. MatsudaNMN. Matsuda
- S. YanagiyaSYS. Yanagiya
- S. HirakiSHS. Hiraki
- S. YasudaSYS. Yasuda
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 300-302