A jitter-tolerant 4.5 Gb/s CMOS interconnect for digital display

Authors:
  • KLK. Lee
    K. Lee
  • SKS. Kim
    S. Kim
  • YSY. Shin
    Y. Shin
  • DJD.-K. Jeong
    D.-K. Jeong
  • GLG. Lim
    G. Lim
  • BKB. Kim
    B. Kim
  • VCV. Da Costa
    V. Da Costa
  • DLD. Lee
    D. Lee
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Abstract
The digital display interface for flat panels is an emerging field that requires a robust high-speed interface for uncompromised picture quality, low cost, and low electromagnetic interference (EMI) in contrast to a very-wide digital-parallel interface. For a high-resolution display such as 1280/spl times/1024 pixels, more than 3.4 Gb/s of aggregate bandwidth is required over a 10 m cable. Since most graphic controllers synthesize the pixel clock to support various display resolutions, the pixel clock jitter exceeds more than 2 ns and the problem is further aggravated. The authors present an interconnect method for minimizing the effects of jitter in the pixel clock, thus improving the robustness of data recovery. The interconnect, comprising a transmitter and receiver, is fabricated with a 0.35 /spl mu/m CMOS process. A 100-pin TQFP package is used for both transmitter and receiver. Author(s) Lee, K. Silicon Image, Cuperlino, CA, USA Kim, S. ; Shin, Y. ; Jeong, D.-K. ; Lim, G. ; Kim, B. ; Da Costa, V. ; Lee, D.

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