Abstract
A sub-GHz/2.4 GHz highly selective reconfigurable RF front-end employing $N$ -path complementary balun-LNA and linearized RF-to-BB current-reuse (CR) mixer is proposed to implement internet-of-things (IoT) devices supporting short-and long-range wireless connectivity technologies. The proposed balun-LNA is built based on an active feedback common-source (CS) amplifier with a common-gate common-source (CGCS) balun load. A complementary version is devised to avoid a severe voltage drop across the resistor load attaining sufficiently high gain and increased effective transconductance without additional current consumption. In addition, an 8-path notch filter is added at a feedback path to improve LNA selectivity in sub-GHz. At 2.4 GHz, an inductive source degenerated LNA (ISDLNA) is used to achieve low noise figure (NF). The proposed RF-to-BB current-reuse mixer employed a second-order-intermodulation (IM2) injection technique for the linearization of the RF front-end. The IM2 injection technique improves linearity by generating the in-phase fundamental signal and out-of-phase third-order-intermodulation (IM3) signal, compared to the passive mixer output. The auxiliary path for the linearization is designed to consume ultra-low power by employing a newly proposed current-reuse-based differential IM2 generator, passive multiplier, and current-steering-based summing stage. As a result, the proposed RF-to-BB CR mixer alleviates the loading effect for the balun-LNA while achieving better gain, NF, and linearity with low power consumption. In measurement, the proposed front-end achieved the conversion gain of 50.5 $\sim$ 44.4 dB and 39.4 dB and double-sideband noise figure (NF $_{\mathrm{DSB}})$ of 4.4 $\sim$ 5.7 dB and 5.3 dB, respectively, in sub-GHz and 2.4 GHz. It also achieved in-band and out-of-band input-referred third-order intercept point (IIP3) from $-$ 18.0 to $-$ 15.2 dBm and from $-$ 0.4 to $-$ 2.6 dBm in sub-GHz and, the in-band IIP3 of $-$ 15.0 dBm at 2.4 GHz. The chip area of the proposed RF front-end core was less than 1.3 mm $^{2}$ excluding the measurement buffer and I/O PADs.
Funding Information
  • National Research Foundation of Korea
  • Korean Government [Ministry of Science and ICT (MIST)] (2021R1A4A1032234, 2022R1A2C2011267)
  • Integrated Circuit Design Education (IDEC), South Korea

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